Jawad Saied Ahmed

01

Profile · The journey starts

Engineering from abstraction to silicon

I'm an Electrical Engineering graduate from Tel Aviv University, specializing in digital hardware design, semiconductor circuit design and the full VLSI design flow — RTL in Verilog, full-custom layout in Cadence Virtuoso, and FPGA integration and bring-up.

My academic work covers the complete chip stack: an ALU taken from logic gates to a DRC/LVS-clean physical layout, a DLX microprocessor brought up on a new FPGA platform end-to-end (RTL, toolchain migration, host software, on-hardware validation), and OTA amplifiers designed to seven simultaneous performance specifications.

Beyond the lab: I led a security team across multiple shifts under operational pressure, and I compete in kickboxing at championship level — both taught me ownership, discipline and calm under deadline. I work comfortably across Arabic, Hebrew and English-speaking teams.

At a glance

LocationTel Aviv, Israel

AvailabilityImmediate · Full-time

FocusChip design · DV · Bring-up

LanguagesArabic · Hebrew · English

EducationB.Sc. EE — TAU · 2026

02

Selected work · The proof

Three projects. Three layers of the chip stack.

Documented the way they're reviewed in industry — problem, approach, verification, result — with the actual design files and a working instrument panel for each. Click any image to zoom. Move your cursor over the images for 3D.

N.001 — Digital VLSI · Front-end to back-end

ALU — Full-Custom VLSI, Schematic to Layout

Cadence Virtuosogpdk45 · 45nmKnowles adderDRC / LVS clean

A complete processor ALU taken from logic gates to verified physical layout in a 45nm PDK.

Built from primitives: synchronous 4/5/6-bit registers (D-FF based) and a parallel-prefix Knowles adder composed from GP, Black and Gray cells.

Extended for subtraction: inverters convert the adder; the output bus widened 5 → 6 bits for correct two's complement.

Signed off: floorplan and routing in Virtuoso, then DRC and LVS passed — layout proven equivalent to schematic.

INTRODUCTION TO VLSI · TEAM OF 4 · FULL REPORT: SCHEMATICS, LAYOUT, VERIFICATION

Live silicon bench — the same ALU datapath UNIT 001 · CLK-GATED · R6 OUT

1

Set the inputs. Tap the bit squares to build numbers A and B (each is a 4-bit register).

2

Pick an operation. ADD or SUB — the same hardware, rerouted through inverters.

3

Pulse CLK ↑. Watch the signal travel the datapath — the result latches only on the clock edge.

A · R4 IN

= 0

B · R4 IN

= 0

OP

OUT · R6

Result: 0 (000000₂) — toggle bits, then pulse CLK.

0

Latched result · signed

The result only latches on the clock edge — like the synchronous D-FF registers in the schematic. Try SUB with B > A for two's complement on the widened 6-bit bus.

N.002 — RTL · HW/SW co-design · Bring-up — Final B.Sc. project #24-1-1-3087

DLX Microprocessor on FPGA — RESA Platform Upgrade

Verilog · VHDLVivado 2024.2Artix-7 · Cmod A7USB-UARTPython

RESA software — registers and memory dump

A university DLX processor flow brought back to life on modern silicon — board, toolchain, RTL and host software.

Migration: legacy Spartan-6 / ISE 14.x flow ported to the Digilent Cmod A7 (Artix-7) on AMD Vivado 2024.2 — one 12 MHz clock domain for the DLX core, memory interface and UART bridge.

My RTL: the processor's I/O logic and bus control in Verilog; BTN0 → RESET, BTN1 → STEP_EN for on-board debug.

Host software: upgraded RESA + a standalone console — memory read/write and control signals (RESET, IN_INIT, STEP_EN) over USB.

Verified: ACSL Labs 1–7 executed end-to-end on real hardware.

TEAM OF 2 · ADVISOR: MORIS ENDER, TAU COMPUTER STRUCTURE LAB · VALIDATED ON HARDWARE

Live bench — RESA console & system map UNIT 002 · 12 MHZ · USB-UART

1

Explore the system. Tap PC / USB-UART / FPGA / SRAM to see what each block does — and which part I built.

2

Send a command. Use the quick buttons or type — e.g. WR 0x10 42 then RD 0x10.

3

Read the response. The simulated FPGA + SRAM answer over the "UART link", just like the real bench.

PCRESA SW ⇄ USB-UARTbridge ⇄ FPGADLX + I/O RTL ⇄ SRAM512 KB

↑ Tap a block to see what it does and which part I built.

RESA>

A miniature of the real console we built — same command set, simulated FPGA + SRAM behind it.

N.003 — Analog design · Trade-off engineering — Grade: 100/100

OTA Amplifier — Seven Specs, Zero Compromises

Cadence VirtuosoPSPICETransistor sizing7 simultaneous specs

Operational Transconductance Amplifiers designed against seven specifications that actively fight each other — more gain costs bandwidth; better phase margin wants compensation that kills GBW; more bias current blows the power budget. Systematic sweeps and iterative transistor re-sizing in Virtuoso closed every target at once: 100/100 in Analog Electronic Circuits.

NO LAB SCREENSHOTS FOR THIS ONE — SO THE DEMO BELOW IS THE PROJECT. CLOSE ALL SEVEN SPECS.

Design lab — close all seven specs UNIT 003 · OTA · SPEC RADAR

1

Drag the sliders. Transistor width, bias current and compensation cap — the 3 knobs of the real design.

2

Watch the radar. Dashed line = spec limit. Your design (solid shape) must clear it on all 7 axes.

3

Close the design. All chips green + gauge at 7/7 = the 100/100 moment. Trade-offs make it hard — that's the point.

INPUT PAIR WIDTH — W/L40 µm

BIAS CURRENT — I_BIAS40 µA

COMPENSATION CAP — C_C3.0 pF

0/7specs closed

Specs met: 0 / 7 — start tuning.

The dashed polygon is the spec limit; the solid shape is your design. Push one slider — watch the shape collapse somewhere else. When the whole polygon clears the dashed line, the design closes. (It took us many Virtuoso iterations.)

RELEVANT TO: MIXED-SIGNAL, AMS VERIFICATION, CUSTOM CIRCUIT ROLES

★

AI-assisted design · The modern flow

AI in the chip-development flow

How does AI actually help build a computer chip? Tap each step to see it in plain terms — then try the live demo below.

AI co-pilot · RTL & verification

Pick a fault to hide in the chip (or leave it clean), then click RUN. The tool tests every possible input against the correct answer, draws the result waveform, scores per-operation coverage, and — if there's a bug — tells you exactly which input broke and why.

0vectors

0mismatches

0%coverage

—verdict

Ready. Choose a fault and click RUN — 1,280 vectors (16×16×5 ops) will be simulated against the golden model.

0%tested

IDLE

Real client-side simulation — testbench, golden model, coverage and waveform computed live. The “AI” writes the plan; engineering owns correctness.

See the co-pilot work — tap a prompt to watch it generate

03

Toolbox · The instruments

Technical skills

A live routing map — every node was used in a real project on this page. Hover or tap a node.

Level:

04

Background · The road here

Education & journey

2022 — 2026 (expected)

B.Sc. Electrical Engineering — Tel Aviv University

GPA 81 · Specialization in digital hardware, semiconductor circuit design and the full VLSI flow. Top grades concentrated exactly where chip design lives:

Analog Electronic Circuits100

Electronic Devices92

Physics 291

Computer Architecture88

Digital Electronic Circuits86

Digital Logic Systems85

Computer Organization85

Introduction to VLSI83

Advanced Computer Lab81

Data Structures & Algorithms81

Leadership

Security Team Leader

Coordinated a team across multiple shifts under operational pressure — ownership, clear communication and reliability when it matters.

Discipline

Competitive Kickboxer — championship level

Consistent training and delivery under pressure; every engineering project shipped to specification.

Self-directed

Beyond the curriculum

Self-taught programming languages and EDA tools beyond formal coursework — iterative design refinement is how the 100/100 happened.